Integrated circuit design involves the creation of electronic components, such as transistors, resistors, capacitors and the metallic interconnect of these components onto a piece of a semiconductor, such as silicon. A typical standard cell based design cycle involves multiple stages such as system specification, architectural design, functional/logic design, circuit design, physical design, physical verification, and fabrication.
The main steps of the physical design stage are floor planning, logic synthesis, placement, clock insertion, routing, and tape out. Placement involves instantiating design component geometric representations (objects) onto a layout area. In practice, the physical design stage is not a straightforward progression and considerable iteration is required to ensure all design objectives (timing, power, area, etc.) are met concurrently.
During timing closure of a standard cell based design, several optimization iterations may be required to resolve a few final setup and hold timing violations. Common design practices include inserting a large number of buffers to resolve hold violations, or replacing standard cells with similar cells that have increased drive-strength to resolve setup violations. Both of these design practices, however, increase the overall layout area requirement of the integrated circuit.